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Global Mixed-mode Technology Inc.
G574
Dual-Slot PCMCIA/CardBus Power Controller
Features
Backward Compatible with G570 Fully Integrated VCC and Vpp Switching for Dual Slot PC CardTM Interface 3-Lead Serial Interface Compatible With CardBusTM Controllers 3.3V Low Voltage Mode Meets PC Card Standards RESET for System Initialization of PC Cards 12V Supply Can Be Disabled Except During 12V Flash Programming Short Circuit and Thermal Protection 30 Pin SSOP Compatible With 3.3V, 5V and 12V PC Cards Low RDS(on) (180-m 5V VCC Switch; 130 m 3.3V VCC Switch) Break-Before-Make Switching Internal power-On Reset Standby mode: 60mA current limit (TYP)
Description
The G574 PC Card power-interface switch provides an integrated power-management solution for two PC Cards. All of the discrete power MOSFETs, a logic section, current limiting, and thermal protection for PC Card control are combined on a single integrated circuit (IC). The circuit allows the distribution of 3.3V, 5V, and/or 12V card power by means of the Serial interface. The currentlimiting feature eliminates the need for fuses, which reduces component count and improves reliability. The G574 features a 3.3V low voltage mode that allows for 3.3V switching without the need for 5V supply. This facilitates low power system designs such as sleep mode and pager mode where only 3.3V is available. The G574 incorporates a reset function, selectable by one of two inputs, to help alleviate system errors. The reset function enables PC card initialization concurrent with host platform initialization, allowing a system reset. Reset is accomplished by grounding the VCC and VPP (flash-memory programming voltage) outputs, which discharges residual card voltage. This device also has the ability to program the xVpp outputs independent of the xVCC outputs. A standby mode that changes all output-current limits to 50mA (typical) has been incorporated. End equipment for the G574 includes notebook computers, desktop computers, personal digital assistants (PDAs), digital cameras and bar-code scanners. The G574 is backward-compatible with the G570.
Application
Notebook PC Electronic Dictionary POS
Ordering Information
PART NUMBER
G574SA
TEMP. RANGE
-40C to +85C
PACKAGE
30 SSOP
Pin Configuration
G 5 74
5V 5V DATA CLOCK LATCH RESET 1 2V AVPP AVCC AVCC AVCC GND NC RESET 3 .3V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5V MODE NC NC NC NC 1 2V BVPP BVCC BVCC BVCC STBY OC 3 .3V 3 .3V
3 0 P in S S O P
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Absolute maximum ratings over operating free-air temperature (unless otherwise noted)*
Input voltage range for card power: VI(3.3V).......................................................-0.3V to 6V VI(5V)........................................................-0.3V to 6V VI(12V)...................................................... -0.3V to 14V Logic input voltage......................................-0.3V to 6V Output current (each card): IO (xVCC)................................................internally limited IO(xVPP)................................................. internally limited
G574
Operating virtual junction temperature range, TJ .......................................................-40C to 125C Operating free-air temperature range, TA .......................................................-40C to 85C Storage temperature range, TSTG..........-55C to 150C Thermal resistance JA SSOP 30.................................................122C/W Power dissipation PD (TA +25C) SSOP 30................................................1024mW ESD...........................................................Note1
*Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device. These are stress rating only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions"is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Note 1: ESD (electrostatic discharge) sensitive device. Proper ESD precautions are recommended to avoid performance degradation or less of functionality.
Recommended Operating Conditions
Min
Input voltage range, VI VI (5V) VI (3.3V) VI (12V) IO (xVCC) at 25C IO (xVPP) at 25C 0 -40 2.7 2.7
Max
5.25 5.25 13.5 1 150 2.5 125
Unit
V V V A mA MHz C
Output current Clock frequency
Operating virtual junction temperature, TJ
Typical PC Card Power-Distribution Application
AVCC 12V 0 .1 F (C e ra m ic ) 10F 12V 12V AVCC AVCC BVCC BVCC BVCC
0 .1 F
V CC V CC V PP1 V PP2 P C C a rd C o n n e c to r A
0 .1 F
V CC P C C a rd V P P 1 C o n n e c to r B V PP2 V CC
5V 0 .1 F (C e ra m ic ) 3 .3 V 0 .1 F (C e ra m ic ) 33F 33F
5V 5V 5V 3 .3 V 3 .3 V 3 .3 V
G 574
AVPP
0 .1 F
BVPP
0 .1 F
DATA CLOCK LATCH RESET RESET OC GND S y s te m V o lta g e S u p e rv is o r or P C I Bus R eset
DATA CLOCK LATCH P C M C IA C o n tro lle r G P I/O
MODE STBY
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Terminal Functions
TERMINAL NAME
3.3V 5V 12V AVCC AVPP BVCC BVPP GND MODE
OC
G574
NO.
15,16,17 1,2,30 7,24 9,10,11 8 20,21,22 23 12 29 18 6 14
I/O
I I I O O O O I O I I 3.3V VCC input for card power
DESCRIPTION
5V VCC input for card power and/or chip power 12V VPP input for card power Switched output that delivers 0V, 3.3V, 5V or high impedance to card Switched output that delivers 0V, 3.3V, 5V, 12V or high impedance to card Switched output that delivers 0V, 3.3V, 5V or high impedance Switch output that delivers 0V, 3.3V, 5V, 12V or high impedance Ground G570 operation when floating or pulled low; must be pulled high externally for G574 operation. MODE is internally pulled low with a 150k pulldown resistor. Logic-level overcurrent. reports output that goes low when an overcurrent condition exists Logic-level reset input active high. Do not connect if RESET pin is used. RESET is internally pulled low with a 150k pulldown resistor. Logic-level reset input active low. Do not connect if RESET pin is used. The pin is internally pulled high with a 150k pullup resistor to 5V, if 5V VCC exists. And pulled to 3.3V, if 3.3V VCC exists only.
RESET
RESET
STBY
19
Logic-level active low input sets the G574 to standby mode and sets all current limits to 50mA. The pin is internally pulled high with a 150k pullup resistor to 5V, if 5V VCC exists. And pulled to 3.3V, if 3.3V VCC exists only.
CLOCK DATA LATCH NC
4 3 5 13,25,26, 27,28
I I I
Logic level clock for serial data word Logic level serial data word Logic level latch for serial data word No internal connection
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Electrical Characteristics
G574
MIN TYP
150 100 110 3 2.9 1.3 1.2 12 5 0.18 0.13 0.3 0.3 6 110 5 82 0 17 2 0.8 120 55 70 44 78 60 155 10
(TA=TJ =25C, VI(5V)=5V, VI(3.3V)=3.3V, VI(12V)=12V, STBY floating, all outputs unloaded (unless otherwise noted) DC Characteristics PARAMETER
5V to xVCC 3.3V to xVCC 3.3V to xVCC 5V to xVPP 3.3V to xVPP 12V to xVPP 3.3V/5V to xVCC 3.3V/5V to xVPP 12V to xVPP
TEST CONDITIONS
VI(5V) = 5V, VI(3.3V) =3.3V VI(5V) = 0V, VI(3.3V) =3.3V
MAX UNIT
180 130 150 4 4 2 2 12.5 6.5 0.8 0.8 1 1 15 150 15 150 45 1 10 1 2.2 450 120 120 120 120 110 m
Switch resistance*
STBY = low, IO = 30mA
V V A A
VO(xVPP) Clamp low voltage VO(xVCC) Clamp low voltage IIKG Leakage current IPP high impedance State ICC high-impedance State II(3.3V) II(5V) II(12V) II(3.3V) II(5V) II(12V) II(3.3V) II(5V) II(12V)
IPP at 10mA ICC at 10mA TA = 25C TA = 25C VO(xVCC) = VO(xVCC) = 5V VI(5V) = 0, VO(xVCC) = 3.3V VO(xVPP) = 12V VO(xVCC) = Hi-Z, VO(xVPP) = Hi-Z Output powered into a short to GND TJ = 25C Output powered into a short to GND
STBY =0V
Normal operation and in reset mode II Input current
A
Shutdown mode
A A mA
IOS Short-circuit* Output current Limit
Thermal shutdown
IO(xVCC) IO(xVPP) Standby mode, 3.3V to xVCC Standby mode, 5V to xVCC Standby mode, 3.3V to xVPP Standby mode, 5V to xVPP Standby mode, 12V to xVPP Trip point, TJ Hysteresis
mA
C
* Pulse-testing techniques are used to maintain junction temperature close to ambient temperatures; thermal effects must be taken into account separately. Input currents do not include logic input currents (presented in electrical characteristics for logic section); clock is inactive. Specified by design, not tested in production.
Logic Section PARAMETER
II (RESET) or ( RESET )* Logic input current II (MODE)* II ( STBY )
*
TEST CONDITION
VI(RESET) = 5V or VI ( RESET ) = 0V VI(RESET) = 0V or VI ( RESET ) = 5V VI(MODE) = 5V VI(MODE) = 0V VI ( STBY )= 5V VI ( STBY )= 0V
MIN
TYP
35 35
MAX
50 1 50 1 1 50 1
UNIT
A
35
II(CLOCK) or II(DATA) or II (LATCH) Logic input high level Logic input low level Logic output high level, OC Logic output low level, OC VI(5V) = 5V, IO = 1mA VI(5V) = 0V, IO = 1mA IO = 1mA
2 2 VI(5V)0.4 VI(3.3V)0.4
0.8
V V V
0.4
V
*RESET and MODE have internal 150k pulldown resistors; RESET and STBY have internal 150k pullup resistors.
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Switching Characteristics *, ** PARAMETER
tr tf Output rise time Output fall time VO (xVCC) VO (xVPP) VO (xVCC) VO (xVPP) LATCHto VO(xVPP) Propagation delay (see Figure 1) LATCHto VO(xVCC) (3.3V), VI(5V) = 5V LATCHto VO(xVCC) (5V) LATCHto VO(xVCC) (3.3V), VI(5V) = 0V
* Refer to Parameter Measurement Information **Switching Characteristics are with CL = 0.1F
G574
MIN TYP
2 1 0.01 0.01 0.2 1.8 2.4 8.5 1 8.5 2.6 8.2
TEST CONDITION
MAX
UNIT
ms
tpd
ton toff ton toff ton toff ton toff
ms ms ms ms
Parameter Measurement Information
xVPP IO(xVPP)
xVCC IO(xCC)
LOAD CIRCUIT
VDD
50%
VDD
50%
LATCH tpd(off) tpd(on) VO(xVPP)
90% 10%
GND
LATCH tpd(off) tpd(on)
90% 10%
GND
GND
VO(xVCC)
GND
Propagation Delay (xVPP) tr VO(xVPP)
90% 10%
Propagation Delay (xVCC) tr GND VO(xVCC)
90% 10%
tf
tf
GND
Rise/Fall Time (xVPP)
Rise/Fall Time (xVCC) VDD
VDD
50%
50%
LATCH toff ton VO(xVPP)
90% 10%
GND
LATCH toff ton
90% 10%
GND
GND
VO(xVCC)
GND
Turn on/off Time (xVPP)
Turn on/off Time (xVCC)
VOLTAGE WAVEFORMS
Figure 1. Test Circuits and Voltage Waveforms
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DATA
G574
D2 D1 D0 Latch Delay Time
D10
D9
D8
D7
D6
D5
D4
D3
Data Setup Time
Data Hold Time
LATCH
Clock Delay Time
CLOCK
Note: Data is clocked in on the positive edge of the clock. The positive edge of the latch signal should occur before the next positive edge of the clock. For definition of D0 to D10, see the control logic table. Figure 2. Serial-Interface Timing for Independent xVPP Switching When MODE=5V or 3.3V
DATA
D8
D7
D6
D5
D4
D3
D2
D1
D0
Data Setup Time
Data Hold Time
Latch Delay Time
LATCH
Clock Delay Time
CLOCK
Note: Data is clocked in on the positive edge of the clock. The positive edge of the latch signal should occur before the next positive edge of the clock. For definition of D0 to D8, see the control logic table. Figure 3. Serial-Interface Timing When MODE = 0V or Floating
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Switching Characteristics
G574
Switching Characteristics
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G574
Switching Characteristics
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Application Information
Overview PC Cards were initially introduced as a means to add EEPROM (flash memory) to portable computers with limited on-board memory. The idea of add-in cards quickly took hold; modems, wireless LANs, Global Positioning Satellite (GPS), multimedia, and hard-disk versions were soon available. As the number of PC Card applications grew, the engineering community quickly recognized the need for a standard to ensure compatibility across platforms. To this end, the PCMCIA was established, comprised of members from leading computer, software, PC Card, and semiconductor manufactures. One key goal was to realize the "plug-and play" concept. Cards and hosts from different vendors should be compatible -- able to communicate with one another transparently. PC Card Power Specification System compatibility also means power compatibility. The most current set of specifications (PC Card Standard) set forth by the PCMCIA committee states that power is to be transferred between the host and the card through eight of the 68 terminals of the PC Card connector. This power interface consists of two VCC, two VPP, and four ground terminals. Multiple VCC and ground terminals minimize connector-terminal and line resistance. The two VPP terminals were originally specified as separate signals but are commonly tied together in the host to form a single node to minimize voltage losses. Card primary power is supplied through the VCC terminals; flash-memory programming and erase voltage is supplied through the VPP terminals. Overcurrent and Over-Temperature Protection PC Cards are inherently subject to damage that can result from mishandling. Host systems require protection against short-circuited cards that could lead to power supply or PCB-trace damage. Even systems robust enough to withstand a short circuit would still undergo rapid battery discharge into the damaged PC Card, resulting in the rather sudden and unacceptable loss of system power. Most hosts include fuses for protection. However, the reliability of fused systems is poor, as blown fuses require troubleshooting and repair, usually by the manufacturer. The G574 takes a two-pronged approach to overcurrent protection. First, instead of fuses, sense FETs monitor each of the power outputs. Excessive current generates an error signal that linearly limits the output current, preventing host damage or failure. Sense FETs, unlike sense resistors or polyfuses, have an added advantage in that they do not add to the series
G574
resistance of the switch and thus produce no additional voltage losses. Second, when an overcurrent condition is detected, the G574 asserts a signal at OC that can be monitored by the microprocessor to initiate diagnostics and/or send the user a warning message. In the event that an overcurrent condition persists, causing the IC to exceed its maximum junction temperature, thermal-protection circuitry activates, shutting down all power outputs until the device cools to within a safe operating region. 12V Supply Not Required Most PC Card switches use the externally supplied 12V VPP power for switch-gate drive and other chip functions, which requires that power be present at all times. The G574 offers considerable power savings by using an internal charge pump to generate the required higher voltages from 5V or 3.3V input; therefore, the external 12V supply can be disable except when needed for flash-memory functions, thereby extending battery lifetime. Do not ground the 12V input if the 12V input is not used. Additional power savings are realized by the G574 during a software shutdown in which quiescent current drops to a typical of 2A. 3.3V Low Voltage Mode The G574 operates in 3.3V low voltage mode when 3.3V is the only available input voltage (VI(5V)=0, VI(12V)=0).This allows host and PC Cards to be operated in low power 3.3V only modes such as sleep modes or pager modes. Note that in this operation mode, the G574 derives its bias current from the 3.3V input pin and only 3.3V can be delivered to the Card. The 3.3V switch resistance increases, but the added switch resistance should not be critical, because only a small amount of current is delivered in this mode. Voltage Transitioning Requirement PC Cards, like portables, are migrating from 5V to 3.3V to minimize power consumption, optimize board space, and increase logic speeds. The G574 is designed to meet all combinations of power delivery as currently defined in the PCMCIA standard. The latest protocol accommodates mixed 3.3V/5V systems by first powering the card with 5V, then polling it to determine its 3.3V compatibility. The PCMCIA specification requires that the capacitors on 3.3V compatible cards be discharged to below 0.8 V before applying 3.3V power. This ensures that sensitive 3.3V circuitry is not subjected to any residual 5V charge and functions as a power reset. The G574 offer a selectable VCC and VPP ground state, in accordance with PCMCIA 3.3V/5V switching specifications, to fully discharge the card capacitors while switching between VCC voltage.
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Shutdown Mode In the shutdown mode, which can be controlled by bit D8 of the input serial DATA word, each of he xVCC and xVPP outputs is forced to a high-inpedance state. In this mode, the chip quiescent current is limited to 2A or less to conserve battery power. Standby Mode The G574 can be put in standby mode by pulling STBY low to conserve power during low-power operation. In this mode, all of the power outputs (xVCC and xVPP) will have a nominal current limit of 50mA. STBY has an internal 150 k pullup resistor. The output-switch status of the device must be set, allowing the output capacitors to charge, prior to enabling the standby mode. Changing the setting of the output switches with the device in standby mode may cause an overcurrent response to be generated. Mode The mode pin programs the switches in either G574 or G570 mode. An internal 150 k pulldown resistor is connected to the pin. Floating or pulling the mode pin low sets the switches in G570 mode; pulling the mode pin high sets the switches in G574 mode. In G570mode, xVPP outputs are dependent on xVCC outputs. In G574 mode, xVPP is programmed independent of xVCC. Refer to G574 control-logic tables for more information. Output Ground Switches Several PCMCIA power distribution switches on the market do not have an active grounding FET switch. These devices do not meet the PC Card specification requiring a discharge of VCC within 100ms. PC Card resistance can not be relied on to provide a discharge path for voltages stored on PC Card capacitance because of possible high impedance isolation by power management schemes. A method commonly shown to alleviate this problem is to add to the switch output an external 100k resistor in parallel with the PC Card. Considering that this is the only discharge path to ground, a timing analysis show that the RC time constant delays the required discharge time to more than 2 seconds. The only way to ensure timing compatibility with PC Card standards is to use a power-distribution switch that has an internal ground switch, like that of the G574, or add an external ground FET to each of the output lines with the control logic necessary to select it. In summary, the G574 is a complete single-chip dual-slot PC Card power interface. It meets all currently defined PCMCIA specifications for power delivery in 5V, 3.3V, and mixed systems, and offers a serial control interface. The G574 offers functionality, power savings, overcurrent and thermal protection, and fault reporting in one 30 pin SSOP surface-mount package for maximum value added to new portable designs.
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G574
Power Supply Considerations The G574 has multiple pins for each of its 3.3V, 5V, and 12V power inputs and for switched VCC outputs. Any individual pin can conduct the rated input or output current. Unless all pins are connected in parallel, the series resistance is significantly higher than that specified, resulting in increased voltage drops and lost power. Both 12V inputs must be connected for proper VPP switching; it is recommended that all input and output power pins be paralleled for optimum operation. Although the G574 is fairly immune to power input fluctuations and noise, it is generally considered good design practice to bypass power supplies typically with a 1F electrolytic or tantalum capacitor paralleled by a 0.047F to 0.1F ceramic capacitor. It is strongly recommended that the switched VCC and VPP outputs be bypassed with a 0.1F or larger capacitor; doing so improves the immunity of the G574 to electrostatic discharge (ESD). Care should be taken to minimize the inductance of PCB traces between the G574 and the load. High switching currents can produce large negative-voltage transients, which forward biases substrate diodes, resulting in unpredictable performance. Similarly, no pin should be taken below -0.3V. RESET or RESET Inputs To ensure that cards are in a known state after power brownouts or system initialization, the PC Cards should be reset at the same time as the host by applying a low impedance to the xVCC and xVPP terminals to ground. A low impedance output state allows discharging of residual voltage remaining on PC Card filter capacitance, permitting the system (host and PC Cards) to be powered up concurrently. The RESET or RESET input will closes internal switches S1, S4, S7, and S11 with all other switches left open (see G574 control logic table). The G574 remains in the low impedance output state until the signal is deasserted and further data is clocked in and latched. RESET or RESET are provided for direct compatibility with systems that use either an active-low or active-high reset voltage supervisor. The unused pin is internally pulled up or down and should be left unconnected. Overcurrent and Thermal Protection The G574 uses sense FETs to check for overcurrent conditions in each of the VCC and VPP outputs. Unlike sense resistors or polyfuses, these FETs do not add to the series resistance of the switch; therefore, voltage and power losses are reduced. Overcurrent sensing is applied to each output separately. When an overcurrent condition is detected, only the power output affected is limited; all other power outputs continue to function normally. The OC indicator, normally a logic high, is a logic low when any overcurrent condition is detected, providing for initiation of system diagnostics and/or sending a warning message to the user.
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During power up, the G574 controls the rise time of the VCC and VPP outputs and limits the current into a faulty card or connector. If a short circuit is applied after power is established (e.g., hot insertion of a bad card), current is initially limited only by the impedance between the short and the power supply. In extreme cases, as much as 10A to 15A may flow into the short before the current limiting of the G574 engages. If the VCC or VPP outputs are driven below ground, the G574 may latch nondestructively in an off state. Cycling power will reestablish normal operation. Overcurrent limiting for the VCC outputs is designed to activate, if powered up, into a short in the range of 0.8A to 2.2A. The VPP outputs limit from 120mA to 450mA. The protection circuitry acts by linearly limiting the current passing through the switch rather than initiating a full shutdown of the supply. Shutdown occurs only during thermal limiting. Thermal limiting prevents destruction of the IC from overheating if the package power-dissipation ratings are exceeded. Thermal limiting disables all power outputs (both A and B slots) until the device has cooled.
G574
Logic Input and Outputs The serial interface consists of DATA, CLOCK, and LATCH leads. The data is clocked in on the positive leading edge of the clock (see Figure 2 and 3 ). The bit (D0 through D10 serial data word is loaded during the positive edge of the latch signal. The latch signal should occur before the next positive leading edge of the block. The shutdown bit of the data word places all VCC and VPP outputs in a high-impedance state and reduces chip quiescent current to 2A to conserve battery power. The G574 serial interface is designed to be compatible with serial-interface PCMCIA controllers and current PCMCIA and Japan Electronic Industry Development Association (JEIDA) standards. An overcurrent output ( OC ) is provided to indicate an overcurrent condition in any of the VCC or VPP outputs as previously discussed.
Functional Block Diagram
G574
3.3V 3.3V 3.3V 15 16 17 S2
CS
9 10 S1 11
A VCC A VCC A VCC
S7
8
A VP P
S3
CS CS
S8
S9
CS
S 10 5V 5V 5V 1 2 30 S5
CS CS
20 21 22
B VCC B VCC B VCC
S4
S 11 S6
CS
23
B VP P
S 12
CS
12V 12V
7
S 13
CS
24
S 14
CS
Internal Current M onitor 29 19 3 4 5 6 14 18 M O DE S TBY DA TA CLOC K LATC H RE SE T RE SE T OC
Therm al
G ND
12
B oth 12V pins m ust be connected together.
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G574 control logic
G574 mode (MODE pulled high) xVPP AVPP CONTROL SIGNALS
D8 ( SHDN ) 1 1 1 1 1 0 D0 0 0 0 1 1 x D1 0 1 1 0 1 x D9 x 0 1 x x x
G574
OUTPUT V_BVPP
0V 3.3V 5V 12V Hi-Z Hi-Z
OUTPUT V_AVPP
0V 3.3V 5V 12V Hi-Z Hi-Z
BVPP CONTROL SIGNALS
D8 ( SHDN ) 1 1 1 1 1 0 D4 0 0 0 1 1 x D5 0 1 1 0 1 x D10 x 0 1 x x x
xVCC
D8 ( SHDN ) 1 1 1 1 0
AVCC CONTROL SIGNALS OUTPUT V_AVCC D3 D2
0 0 1 1 x 0 1 0 1 x 0V 3.3V 5V 0V Hi-Z
BVCC CONTROL SIGNALS
D8 ( SHDN ) 1 1 1 1 0 D6 0 0 1 1 x D7 0 1 0 1 x
OUTPUT V-BVCC
0V 3.3V 5V 0V Hi-Z
G570 mode (MODE floating or pulled low) xVPP AVPP CONTROL SIGNALS
D8 ( SHDN ) 1 1 1 1 0 D0 0 0 1 1 x D1 0 1 0 1 x
OUTPUT V_AVPP
0V V_AVCC 12V Hi-Z Hi-Z
BVPP CONTROL SIGNALS
D8 ( SHDN ) 1 1 1 1 0 D4 0 0 1 1 x D7 0 1 0 1 x
OUTPUT V-BVPP
0V V_BVCC 12V Hi-Z Hi-Z
xVCC
D8 ( SHDN ) 1 1 1 1 0
AVCC CONTROL SIGNALS OUTPUT V_AVPP D3 D2
0 0 1 1 x 0 1 0 1 x 0V 3.3V 5V 0V Hi-Z
BVCC CONTROL SIGNALS
D8 ( SHDN ) 1 1 1 1 0 D6 0 0 1 1 x D7 0 1 0 1 x
OUTPUT V-BVPP
0V 3.3V 5V 0V Hi-Z
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ESD Protection
The xVCC and xVPP outputs can be exposed to potentially higher discharges from the external environment
G574
through the PC Card connector. Bypassing the outputs with 0.1F capacitors protects the devices from discharges up to 10 kV.
AVCC 12V 0.1F (Ceramic) 10F 12V 12V AVCC AVCC BVCC BVCC BVCC
0.1F
VCC VCC VPP1 VPP2 PC Card Connector A
0.1F
VCC PC Card VPP1 Connector B VPP2 VCC
5V 0.1F (Ceramic) 3.3V 0.1F (Ceramic) 33F 33F
5V 5V 5V 3.3V 3.3V 3.3V
G574
AVPP
0.1F
BVPP
0.1F
DATA CLOCK LATCH RESET RESET OC GND System Voltage Supervisor or PCI Bus Reset
DATA CLOCK LATCH PCMCIA Controller GPI/O
MODE STBY
Figure 3. Detailed Interconnections and Capacitor Recommendations
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G574 30Pin Package
D c L1 L
G574
E1 1 .1 5
E
3 .6
A1
A
e
b
A2
Note: 1. Dimensional tolerance 0.10mm 2. Plating thickness 5~15m 3. Dimensions "D" does not include burrs, however dimension including protrusions or gate burrs Shall be MAX. 0.20mm 4. Dimension "E1" does not include inter-lead flash or protrusion. Inter-lead flash or protrusion small not exceeds 0.25 per side. SYMBOL
A A1 A2 b C D E E1 L1 L e
MIN.
1.80 1.75 0.05 0.25 0.10 10.10 7.50 5.20 0.53 1.10 1
DIMENSION IN MM NOM.
1.90 1.80 0.10 0.30 0.15 10.15 ----5.25 0.68 1.20 0.65 BSC 4
MAX.
2.00 1.85 0.15 0.35 0.20 10.20 7.90 5.30 0.83 1.30 7
MIN.
0.071 0.069 0.002 0.010 0.004 0.398 0.295 0.205 0.021 0.043 1
DIMENSION IN INCH NOM.
0.075 0.071 0.004 0.012 0.006 0.400 ----0.207 0.027 0.047 0.026BSC 4
MAX.
0.079 0.073 .006 0.014 0.008 .402 0.311 0.209 0.033 0.051 7
Taping Specification
Feed Direction Typical SSOP Package Orientation
GMT Inc. does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and GMT Inc. reserves the right at any time without notice to change said circuitry and specifications.
Ver: 1.0 Jan 23, 2003
TEL: 886-3-5788833 http://www.gmt.com.tw
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